HV 65V nLDMOSs Engineering of ESD Enhancement by the Drain Side with Parasitic SCR Modulations

Abstract

In this paper, a parasitic silicon controlled rectifier (SCR) area modulation at the drain-side of high-voltage n-type laterally-diffused metal-oxide semiconductor(nLDMOS) is proposed to evaluate the change of electrostatic discharge+ (ESD) capability with the increasing of SCR area. As the P doping area of the drain side is larger, the SCR characteristics are more obvious. Therefore, it can be found from the experimental data that when the P+ doping area is 100% (the nLD_SCR_P100), the It2 value of the device will increase from 1.38 A of the reference device to 9 A (an increase of 652.1%). Although the Vt1 and Vh values of the device also decreaseIt2, slightly as the SCR area becomes larger, but it has the best so the FOM increases from 1659.13 µA×V/µm2 for the reference device to 8098.56 µA×V/µm2(an increase of 488.1%), the ability to conduct ESD current is significantly improved.