Range segmentation to improve latency in parallel stochastic computing

Abstract

Stochastic Computing (SC) is a fault tolerant design paradigm where numeric data are converted to probabilities on streams of random digital bits. This representation allows computing on low complexity hardware. SC allows a significant area reduction and an increased tolerance to transient errors, but presents high latency to achieve a moderate accuracy. Recent papers address this issue using parallelism and stochastic multibit number representations. In this paper, Multilevel Stochastic Coding (MSC), a new stochastic representation based on range segmentation is presented and its operators are developed using FPGA design flow and compared to alternative approaches. A comparison in terms of area and latency is applied between approaches to achieve a given signal to noise ratio (SNR). Results show that MSC presents a significant latency reduction with a smaller area penalty.