Verification of soft error detection mechanism through fault injection on hardware emulation platform

Abstract

In this paper we describe one of the verification activities performed on a dual core 32-bit System-on-Chip designed for Automotive Safety applications and the consequent implementation of a methodology to verify the functionality of one of the safety mechanisms of the device. The Safety standards recommend the usage of fault-injection techniques to give evidence of the failure robustness of the electronic devices designed for Functional Safety. In this case we verified the robustness of the SoC processing subsystem to the Single Event Upset through the usage of some hardware emulation platforms where the device RTL was mapped, properly instrumented to allow the modification of Flip-Flop status during application runtime, thus modeling the SEUs effects. The main novelty of our work is therefore the definition of a methodology to verify the robustness of a SoC to SEUs; additionally we show that the same methodology can be used also to perform thorough measurements of the SER masking effect on a System on Chip.