Design and implementation of four bit arithmetic and logic unit using hybrid single electron transistor and MOSFET at 120nm technology

Abstract

Low power design requires optimization at all levels and recent development in nanoscale devices unlock the idea of hybridization due to which power consumption of a system can be controlled. The implementation of hybrid techniques for the designing of four bit arithmetic and logic unit with low power dissipation is presented in these paper. The characteristics of SET as a low power device and MOSFET as a high speed device produces unique innovations, which is not possible to achieve with only CMOS circuit. The basic hybrid gates designed and simulated as well as new XOR gate is designed for reducing the power dissipation in implementation of four bit hybrid arithmetic and logic unit. Three different full adders designed, simulated and compared in terms of power dissipation.