{"title":"UF/sup 3/-a 4-D DSP hypercube with a robust programming environment","authors":"Ahmad R. Ansari, F. Taylor","doi":"10.1109/ICASSP.1992.226541","DOIUrl":null,"url":null,"abstract":"The UF/sup 3/ is a 4-D hypercube multiprocessor system which is integrated with an innovative programming environment. The architecture of UF/sup 3/ contains fully programmable nodes which allow use of the system to address problems with arbitrary entities. The self-scheduling programming environment of UF/sup 3/ uses its bottom-up approach to balance the workload among the processors. The architecture provides the digital signal processor (DSP) community with a high-bandwidth general-purpose accelerator array having a high degree of computational accuracy and a robust programming environment. The principal application of the UF/sup 3/ is serving the numerically intensive computational needs of the DSP community.<<ETX>>","PeriodicalId":163713,"journal":{"name":"[Proceedings] ICASSP-92: 1992 IEEE International Conference on Acoustics, Speech, and Signal Processing","volume":"45 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"[Proceedings] ICASSP-92: 1992 IEEE International Conference on Acoustics, Speech, and Signal Processing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICASSP.1992.226541","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
The UF/sup 3/ is a 4-D hypercube multiprocessor system which is integrated with an innovative programming environment. The architecture of UF/sup 3/ contains fully programmable nodes which allow use of the system to address problems with arbitrary entities. The self-scheduling programming environment of UF/sup 3/ uses its bottom-up approach to balance the workload among the processors. The architecture provides the digital signal processor (DSP) community with a high-bandwidth general-purpose accelerator array having a high degree of computational accuracy and a robust programming environment. The principal application of the UF/sup 3/ is serving the numerically intensive computational needs of the DSP community.<>