Design of low-power and high performance radix-4 multiplier

Abstract

A One-bit adder is designed using modified complementary pass transistor logic (MCPL). The proposed adder is implemented in 4×4 bit high radix multiplier to achieve high speed, low area and less power dissipation. This circuit is simulated by using DSCH2 schematic design tool and layout is taken by Microwind 2 VLSI layout CAD tool, and the analysis is done by using the BSIM4 analyzer. The 4×4 bit high radix multiplier is then compared with Carry Save Array multiplier (CSA multiplier), Baugh-Wooley multiplier, and high radix multiplier to show the better performance in terms of power, area and delay.