Compact outside-rail circuit structure by single-cascode two-transistor topology

A. Tamtrakarn, H. Ishikuro, K. Ishida, T. Sakurai
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引用次数: 1

Abstract

This paper presents a new compact outside-rail circuit structure for future scaled CMOS technology. The proposed circuit is composed of only two transistors connected into a single cascode style for increasing supply voltage to one more nominal supply voltage (VDD ). The circuit is manufactured and measured. Reliability is also verified by the trajectory plot for gate-source voltage and gate-drain voltage of all devices. The results confirm that triple of nominal supply voltage can be used without any overstress in all CMOS devices. The proposed circuit saves 52% area and improves speed for 40% of the conventional approach in the case of 4VDD. An example of outside-rail opamp is also proposed by using the proposed circuit
紧凑的外轨电路结构,单级联双晶体管拓扑结构
本文提出了一种新的紧凑的外轨电路结构,用于未来的规模化CMOS技术。所提出的电路仅由两个晶体管组成,连接成一个级联代码,用于将供电电压增加到一个标称供电电压(VDD)。制作并测量了电路。通过各器件的栅极源电压和栅极漏电压轨迹图验证了可靠性。结果证实,在所有CMOS器件中,可以使用三倍标称电源电压而不会产生任何过应力。在4VDD的情况下,该电路节省了52%的面积,并将速度提高了40%。最后,给出了利用该电路实现外轨运放的一个实例
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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