Design and simulation of three ATM ASICs

AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360) Pub Date : 1999-08-23 DOI:10.1109/APASIC.1999.824019

Chan Kim, J. Jun, Sang Ho Lee, Jae Geun Kim

引用次数: 0

Abstract

In ASIC development, effective simulation leads into functionally more reliable chips as well as faster development time. This paper describes the design and the simulation techniques used in 3 ATM ASIC developments in ETRI. The three ASICs described are: ASAH-NIC-a 155 Mbps ATM SAR chip with internal PCI interface and SDH framer; ASAPI-L4-a 622 Mbps bidirectional ATM layer processing chip with UPC, OAM, QOS buffering capabilities; and ASAH-P4-a 622 Mbps ATM physical layer chip.

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三种ATM专用集成电路的设计与仿真

在ASIC开发中，有效的仿真可以提高芯片的功能可靠性，缩短开发时间。本文介绍了ETRI中3atm专用集成电路的设计和仿真技术。所描述的三种asic分别是:asah - nic -内置PCI接口和SDH帧的155mbps ATM SAR芯片;asapi - l4 -具有UPC、OAM、QOS缓冲能力的622 Mbps双向ATM层处理芯片;和asah - p4 - 622 Mbps ATM物理层芯片。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)

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