A DST Hardware Structure of HEVC

Abstract

HEVC (High Efficiency Video Coding) is a new generation of video coding standard which is proposed by ITU-T VCEG and ISO/IEC MPEG for the increasingly widespread application of high-definition video. On the basis of original DCT transform of H.264, HEVC has proposed a DST transform with the size of 4×4. We design the hardware structure of pipelined DST by analyzing software algorithm, according to the parallel characteristics of the ASIC, only with shifters, addition, counters and 4-2 compression method. After logic synthesis using SMIC 0.13μm standard cell library, simulation results show that the proposed architecture of 4×4 DST logic gates for 7K. The design can meet the demanding of timing sequence under the circumstance of real-time processing of 3840×2160@25fps sequences of images under 300MHz, and is very suitable for VLSI HD encoder.