Digital circuit optimization using Pass Transistor Logic architectures

Abstract

this research paper analyzes optimization of different combinational logic circuits (AND gate, OR gate, multiplexer, de-multiplexer) using Pass Transistor Logic Configuration (PTL) and CMOS Logic Configuration. PTL design used in this paper is significant as gate terminal is only denoting input terminal rather than controlling terminal as in previously reported PTL designs. This technique essentially decreases the number of nodes in the circuit as well as its overall size too. Further, a comparison between the performances of both the configurations in terms of number of transistors utilized in the designing of circuit and chip area has also been done with help of 1∶2 de-multiplexers (de-mux). Besides this, paper also signifies more than 50% decrement in interconnect lengths, chip area and number of transistors count while using pass transistor logic configuration for combinational logic circuit (1∶2 de-multiplexer) in comparison to when implemented through CMOS logic configuration.