Reduction of the Feedback Capacitance of HFETs by Changing Transistor Layout and Using Via Holes for Source Grounding

Abstract

The influence of HFET layout and via holes on the feedback capacitance of passive and non-gated as well as active HFETs has been examined. We have found that by careful design of the layout of the HFET and using via-hole for source grounding it is possible to reduce the feedback capacitance, thus improving the high frequency characteristics of the HFET. The total feedback capacitance was reduced by 70 % for a passive device with via holes and by varying one layout parameter. Results on active InP-based HFETs without via-holes show a total decrease of the feedback capacitance of 40 % for an InAlAs/InGaAs/InP HFET. The maximum stable gain at 40 GHz for an InAlAs/InGaAs/InP HFET. Was increased by 1.5 dB by changing the layout.