3D IC test scheduling with test pads considered

Abstract

As the design complexity increases, three-dimensional (3D) integrated circuit (IC) design has become an industry trend. However, the testing of a 3D IC is a design challenge. In addition to minimize the test application time (including pre-bond testing and post-bond testing), the number of test pads of each layer should also be taken into account. In this paper, we propose an integer linear programming (ILP) approach to perform the 3D IC test scheduling with test pads considered. Different from those previous works, our objective is to minimize the weighted sum of the test application time and the number of required test pads. Experimental results consistently show that our approach works well in practice.