Macromodel Based Fault Simulation of Linear Circuits using Parameter Estimation

Abstract

Fault simulation is one of the elemental steps in test pattern generation and is widely used for digital circuits. In case of analog circuits, fault simulation is not generally adopted because of the lack of suitable fault models and the time required for the transistor level simulation of the entire circuit. In this paper, a macromodel level fault model, which is able to represent the faulty behavior of the linear circuits with opamp, is presented. Macromodel based platform is chosen for fault simulation because, as shown in this paper, they are much faster in simulation than transistor level models but fault behavior is captured within an adequate range of accuracy. The faults considered are mostly parametric and few are catastrophic in nature. For ease of the test engineers, the macromodel parameters of the faulty opamp used for linear circuits are obtained automatically by a parameter estimation tool, given the macromodel of the normal circuit and the fault.