Multiprocessor design using joint transform correlator

Proceedings of the IEEE 1993 National Aerospace and Electronics Conference-NAECON 1993 Pub Date : 1993-05-24 DOI:10.1109/NAECON.1993.290794

M. Alam

引用次数: 0

Abstract

The joint transform correlation technique is used to design a binary multiprocessor that can perform full addition and full subtraction in parallel. A new coding scheme is designed for the proposed technique. Finally, simulation results are presented to verify the effectiveness of the proposed scheme.<>

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采用联合变换相关器的多处理器设计

采用联合变换相关技术设计了一种能够并行进行全加减运算的二进制多处理机。为该技术设计了一种新的编码方案。最后给出了仿真结果，验证了所提方案的有效性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Proceedings of the IEEE 1993 National Aerospace and Electronics Conference-NAECON 1993

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