Schmitt-Trigger-Based Low Power SRAM Implemented Using 45-nm CMOS Technology

Abstract

This paper presents a Schmitt-trigger-based SRAM with a separated read port, which significantly improves read static noise margin (RSNM) and consumes low energy. Post-layout simulation results show that the proposed design performed better than the conventional 6T SRAM cell. The SNM of the designed cell is 1.16 mV higher than the conventional 6T SRAM cell in write mode, and 232.37 mV and 207.46 mV in read mode 1 and 0, respectively. The impact of the process, voltage, and temperature variations on cell performance parameters such as read, write and hold SNM, power per access, power per bit, delay, and energy per bit was investigated. Aside from this, the DNM of the cell was also measured to determine the noise tolerance of the cell during the write operation. Monte Carlo simulation results verified how robust the proposed cell is. The design was implemented in a 45-nm technology in which the cell occupies 4.53×4.53 µm2 and the system is 568.55×568.55 µm2. This cell consumes only 0.396 fJ, which is lower than the energy per bit consumed on the 6T conventional cell which is 7.265 fJ. All-corner simulation results show that the proposed cell is suitable for low-power applications.