On Designing Robust Path-Delay Fault Testable Combinational Circuits Based on Functional Properties

Abstract

Although path-delay faults (PDF) have been studied extensively during the last three decades, design of combinational circuits to achieve low-overhead robust PDF testability, still poses many challenges. In this paper, we revisit the problem of synthesizing a robust path-delay fault testable combinational circuit based on certain new functional properties. Given the boolean cubes of a function, we first design a two-level robust PDF testable circuit by properly grouping the cubes using a few additional control lines. Next, we apply some testability-preserving algebraic factorization techniques to design multi-level circuits. The method readily extends to multi-output circuits as well. Experimental results establish that the proposed functional approach yields fully robust PDF-testable circuits with much lower overhead as compared to earlier approaches.