Circuit implementation of high-speed pipeline systems

L. Cotten
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引用次数: 61

Abstract

The implementation of high-speed pipeline systems as described in this paper arose as a direct consequence of a large scale Department of Defense developmental effort initiated in 1962. The objective of the effort was to develop and make available a complete capability for producing individual special-purpose systems on a fast reaction basis. From 1962 to the present time attention was focused on all aspects of circuit and packaging technology, automated or computerized design aids, feasibility vehicling, systems design studies, and advanced memory development. As a result of strong industry impetus in these directions it now appears that 1 to 2 nanosecond hybrid integrated or full integrated logic circuits, practical fabrication of transmission line interconnections, packaging densities of 5000 logic gates per cubic foot in the machine environment, 100 to 150 nanosecond cycle time DRO thin film main memories, and 23 to 40 nanosecond integrated scratchpad memories will be made available for systems being constructed over the next one to three year period.
电路实现高速管路系统
本文中所描述的高速管道系统的实施是1962年开始的国防部大规模发展努力的直接结果。这项工作的目标是发展和提供在快速反应基础上生产个别特殊用途系统的完整能力。从1962年到现在,注意力集中在电路和封装技术的各个方面,自动化或计算机化设计辅助工具,可行性车辆,系统设计研究和高级存储器开发。由于这些方向的强大工业推动力,现在出现了1到2纳秒混合集成或全集成逻辑电路,传输线互连的实际制造,机器环境中每立方英尺5000个逻辑门的封装密度,100到150纳秒周期时间的DRO薄膜主存储器,23到40纳秒集成的刮刮板存储器将在未来一到三年内用于系统的构建。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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