Low specific on-resistance p-type OPTVLDLDMOS with double hole-conductive paths for SPIC application

Abstract

A novel p-type DP-OPTVLD (Double-Paths & OPTimum-Variational-Lateral-Doping) LDMOS is proposed. It features the double hole-conductive paths formed by a top and a buried p-layer in the drift region using OPTVLD technique, which significantly contribute to reducing device specific on-resistance. The design principle and electrical characteristics of the proposed structure are investigated theoretically and experimentally. Simulation results show that the specific on-resistances are 155/689 mΩ·cm2 with breakdown voltages of 300/800 V for the proposed structure, respectively, which are less than 60% of that with corresponding breakdown voltages for the conventional structure. This structure used as high-side can apply to SPIC with a low integration difficulty and a low fabrication cost.