Novel Ultra Low Power Dual Edge Triggered Retention Flip-Flop for Transiently Powered Systems

Abstract

Emerging sensor based electronic gadgets desire to seek high levels of energy conservation by adopting extreme low power techniques in combination with traditional techniques. In this study the authors examine memory units with data retention capability in the Energy-Delay space for an emerging application namely Transiently Powered System for three levels of power and performance optimization. The study presents a novel Dual Edge Triggered Flip-Flop (DETRFF) with retention latch that is suitable for ultra low power application with dynamic voltage switch between super and sub threshold levels. The DETRFF designs are simulated in 45nm NCSU CMOS technology using Cadence. The proposed design excels in the EDP and Leakage Energy metrics as compared to the existing DETFF designs.