{"title":"Novel ultra low voltage semi floating-gate passband transconductance amplifier","authors":"Y. Berg","doi":"10.1109/MELCON.2010.5476281","DOIUrl":null,"url":null,"abstract":"An ultra low voltage differential transconductance amplifier based on clocked binary and analog iverters is presented. Supply voltages down to 250mV can be applied. Clocked semi-floating-gate binary inverters used for ultra low voltage digital logic are exploted to obtain analog inverting gates. The ultra low voltage amplifier perform a passband operation where the passband is dependent on the applied current level. The gates used resemble precharge CMOS logic where the cuirrent level is determined by offset voltages and the precharge level is determined by the supply voltage provided by the clock signals applied. Simulated data presented are valid for a 90nm STM CMOS process.","PeriodicalId":256057,"journal":{"name":"Melecon 2010 - 2010 15th IEEE Mediterranean Electrotechnical Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Melecon 2010 - 2010 15th IEEE Mediterranean Electrotechnical Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MELCON.2010.5476281","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
An ultra low voltage differential transconductance amplifier based on clocked binary and analog iverters is presented. Supply voltages down to 250mV can be applied. Clocked semi-floating-gate binary inverters used for ultra low voltage digital logic are exploted to obtain analog inverting gates. The ultra low voltage amplifier perform a passband operation where the passband is dependent on the applied current level. The gates used resemble precharge CMOS logic where the cuirrent level is determined by offset voltages and the precharge level is determined by the supply voltage provided by the clock signals applied. Simulated data presented are valid for a 90nm STM CMOS process.