B. Giraud, S. Ricavy, Yasser Moursy, C. Laffond, I. Sever, V. Gherman, M. Pezzin, F. Lepin, M. Diallo, K. Zenati, S. Dumas, M. Vershkov, A. Bricalli, G. Piccolboni, J. Noël, A. Samir, G. Pillonnet, Y. Thonnart, G. Molas
{"title":"Benefits of Design Assist Techniques on Performances and Reliability of a RRAM Macro","authors":"B. Giraud, S. Ricavy, Yasser Moursy, C. Laffond, I. Sever, V. Gherman, M. Pezzin, F. Lepin, M. Diallo, K. Zenati, S. Dumas, M. Vershkov, A. Bricalli, G. Piccolboni, J. Noël, A. Samir, G. Pillonnet, Y. Thonnart, G. Molas","doi":"10.1109/IMW56887.2023.10145984","DOIUrl":null,"url":null,"abstract":"This paper presents different design assist techniques and demonstrates their impact on enhancing the intrinsic RRAM performance. We show that the read-beforewrite, current-limitation and write-termination techniques reduce by -47%, -56% and-13% the power consumption during the writing process, respectively. Combined with write verification and error correction code, the overall improvements are 87% in energy saving and -55% on access time. Based on representative RRAM macro (130nm CMOS), statistic (128kb) and endurance (1M cycles) characterizations, this works contributes to accelerate RRAM industrial adoption by highlighting the design-technology co-optimization contribution.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 IEEE International Memory Workshop (IMW)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMW56887.2023.10145984","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
This paper presents different design assist techniques and demonstrates their impact on enhancing the intrinsic RRAM performance. We show that the read-beforewrite, current-limitation and write-termination techniques reduce by -47%, -56% and-13% the power consumption during the writing process, respectively. Combined with write verification and error correction code, the overall improvements are 87% in energy saving and -55% on access time. Based on representative RRAM macro (130nm CMOS), statistic (128kb) and endurance (1M cycles) characterizations, this works contributes to accelerate RRAM industrial adoption by highlighting the design-technology co-optimization contribution.
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