Conditional Acknowledge Synchronisation in Asynchronous Interconnect Switch Design

Abstract

One of the main challenges in building reconfigurable asynchronous architectures is the design of the reconfigurable interconnect scheme. An asynchronous channel connecting a sender to multiple receivers cannot be split or shared between the receivers without additional complex circuitry to acknowledge every transition on the channel. The technique used in existing asynchronous reconfigurable architectures involves designing the interconnect scheme so that all the tokens have unique senders and receivers; tokens needed by more than one block must first be duplicated. At the duplication stage, the data and request signals of a sender are copied to all receivers. For any given configuration, the resulting acknowledge signals must be synchronised so the sender receives an acknowledge only when the receivers involved in communication have acknowledged its request.In this paper we present a novel method for conditional acknowledge synchronisation in asynchronous interconnects. Compared to the commonly employed synchronising technique, our method results in the design of reconfigurable interconnects which are smaller in area, require less configuration bits, and consume less power. For a sample island-style interconnect, our designs showed a 25% reduction in configuration bits, up to 47% reduction in area and up to 45% reduction in power consumption over equivalent interconnects designed using the traditionally used synchronisation technique.