Modeling and Simulation of Noise in Closed-Loop All-Digital PLLs using Verilog-A

Abstract

The modeling and simulation of an all-digital PLL is presented. Verilog-A, owing to its flexibility, is used to create both behavioral and gate-level models used in system-level and circuit-based simulation. The methodology presented allows us to simulate the PLL closed-loop and accurately take into account reference phase noise, DCO phase noise, quantization noise and any excess of it, allowing us to validate our jitter budget for any given application.