A quad-channel 3.125Gb/s/ch serial-link transceiver with mixed-mode adaptive equalizer in 0.18 /spl mu/m CMOS

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI:10.1109/ISSCC.2004.1332651

Jeongsik Yang, Jinwook Kim, S. Byun, C. Conroy, Beomsup Kim

引用次数: 10

Abstract

This paper presents a quad-channel serial-link transceiver which provides 12.5 Gb/s full duplex raw data rate for a single 10 Gb XAUI interface. A mixed-mode LMS adaptive equalizer is adopted, which achieves 3 dB SNR improvement over pre-emphasis techniques. A delay-immune CDR circuit recovers the receive clock with 64 ps-pp jitter. The IC consumes 718 mW at 3.125 Gb/s/ch with full duplex data rate.

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一种四通道3.125Gb/s/ch串行链路收发器，带有混合模式自适应均衡器，采用0.18 /spl mu/m CMOS

本文提出了一种四通道串行链路收发器，该收发器可为单个10gb XAUI接口提供12.5 Gb/s的全双工原始数据速率。采用混合模式LMS自适应均衡器，比预强调技术提高了3db信噪比。一个延迟免疫CDR电路恢复接收时钟的64 ps-pp抖动。全双工数据速率为3.125 Gb/s/ch，功耗为718 mW。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)

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