8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation

Stephen T. Kim, Y. Shih, K. Mazumdar, Rinkle Jain, J. Ryan, Carlos Tokunaga, C. Augustine, J. Kulkarni, K. Ravichandran, J. Tschanz, M. Khellah, V. De
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引用次数: 37

Abstract

A graphics execution core in 22nm improves energy efficiency across a wide DVFS range, from the near-threshold voltage (NTV) region, where circuit assist lowers intrinsic VM!N, to the turbo region, where adaptive clocking reduces the voltage-droop guard-band [1]. When powered with a shared rail, however, energy is wasted in the core if other blocks demand higher voltage and performance. Alternately, a per-core fully-integrated voltage regulator (VR) provides a cost-effective means to realize autonomous DVFS [2-4]. In this paper, we present a graphics core that is supplied by a fully integrated and digitally controlled hybrid low-drop-out (LDO)/switched-capacitor voltage regulator (SCVR) with fast droop response (Fig. 8.6.1). While the LDO VR enables high power density and is area efficient, as it can use existing power headers originally employed for bypass/sleep modes, it suffers from efficiency loss at low VOUT. An SCVR, on the other hand, has improved conversion efficiency across a wide VOUT range. In an area-constrained design, however, the limited size of the SCVR's fly capacitors and associated configurable power stages sets an upper bound on the SCVR's maximum power density, restricting its use to lower VOUT. This LDO/SCVR combination delivers the power required by the core at a high VOUT of 0.92V with 84% LDO efficiency, while extending to a low VOUT of 0.38V with 52% SCVR efficiency from a 1.05V VIN. Compared to a shared-rail scheme, the hybrid VR enables 26% to 82% reduction in core energy versus 26% to 67% if solely the LDO is used.
8.6使用数字控制混合LDO/开关电容VR在22nm图形执行核心中实现宽自主DVFS,具有快速下垂缓解
22nm的图形执行核心提高了宽DVFS范围内的能量效率,从近阈值电压(NTV)区域开始,电路辅助降低了固有VM!N为turbo区域,自适应时钟降低了电压下降保护带[1]。然而,当使用共享导轨供电时,如果其他块需要更高的电压和性能,则会在核心中浪费能量。另外,一个核心完全集成的电压调节器(VR)提供了一种经济有效的方法来实现自主DVFS[2-4]。在本文中,我们提出了一个图形核心,它由一个完全集成和数字控制的混合低降差(LDO)/开关电容电压调节器(SCVR)提供,具有快速的下降响应(图8.6.1)。虽然LDO VR具有高功率密度和面积效率,因为它可以使用最初用于旁路/休眠模式的现有电源头,但在低VOUT时存在效率损失。另一方面,SCVR在宽VOUT范围内提高了转换效率。然而,在面积受限的设计中,SCVR的飞行电容器和相关的可配置功率级的有限尺寸设置了SCVR的最大功率密度的上限,限制了其用于降低VOUT。这种LDO/SCVR组合在0.92V的高VOUT下提供核心所需的功率,LDO效率为84%,同时从1.05V VIN扩展到0.38V的低VOUT, SCVR效率为52%。与共享轨道方案相比,混合VR可以减少26%至82%的核心能量,而单独使用LDO则可以减少26%至67%的核心能量。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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