A universal self-test design for chip, card and system

Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1992-11-04 DOI:10.1109/DFTVS.1992.224344

D.M. Wu, R. Doney

引用次数: 0

Abstract

Describes an implementation of chip built-in self-test using by-pass boundary scan design. This basic structure is then modified to implement a universal self-test structure for cards, boxes and systems.<>

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一种通用的芯片、卡和系统自检设计

介绍一种采用旁通边界扫描设计的芯片内置自检实现。然后对这个基本结构进行修改，以实现卡片、盒子和系统的通用自检结构

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

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