Store and Restore Delay Reduction Techniques of Non-volatile SRAM cells

Abstract

The incorporation of memristor with static random access memory (SRAM) cell, known as non-volatile SRAM (nvSRAM) cell, not only introduces non-volatile feature in it but also enhances stability and reduces power consumption. With the development in technology, this has become a mainstream development focus. During the analysis of nvSRAM cell, the store and restore delays become a major concern as the longer time duration leads to memory failure. Limited work is done to address this problem, which increases complexity during non-volatile operation. In this work, different techniques are introduced to reduce the store and restore delays. These delay reduction techniques deal with the control signals required to perform non-volatile operation. The maximum reduction of 19.41% is achieved in the store delay, while the restore delay is reduced by 21.74%. The SPICE simulations are carried out using 32nm PTM CMOS model at Vdd=1.0V.