Determine the Interconnection of a Hardware Implementation for DSP Applications

J. Ghanim, A. Shatnawi
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引用次数: 0

Abstract

In VLSI design the hardware is implemented with some objective and constrain functions (as lower number of hardware used). When the system contains a lot of processing elements (PEs) and memory registers, the cost of the interconnections becomes of great issue and must be minimized. The work in the field of determination of the interconnection for a hardware implementation is not very common. In high-level synthesis it is usually considered the time scheduling and processor assignment from a given DFG. However, the cost of interconnection is not widely discussed and is left to a hardware system to determine it. In this paper, a technique for determining the interconnection in a hardware design is proposed. The objective function is the minimum number if hardware used and the constrain is minimum iteration period bound. This interconnection is shown to accomplish cost optimality in terms of minimizing the number of multiplexers used.
确定DSP应用的硬件实现的互连
在VLSI设计中,硬件是用一些目标和约束函数来实现的(因为使用的硬件数量较少)。当系统中包含大量的处理元件和内存寄存器时,互连的成本就成为一个很大的问题,必须最小化互连的成本。在确定硬件实现的互连方面的工作并不常见。在高级综合中,通常考虑给定DFG的时间调度和处理器分配。然而,互连的成本并没有被广泛讨论,而是留给硬件系统来决定。本文提出了一种在硬件设计中确定互连的技术。目标函数是使用硬件的最小数量,约束是最小迭代周期。这种互连被证明在最小化所使用的多路复用器数量方面实现了成本优化。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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