SiP solutions for wireless transceiver impedance matching networks

Abstract

This work proposes the improvement of the RF transceiver front-end based on the integration of passive components using modern SiP technologies. The investigation of two passive impedance matching networks for a SCPA are presented as low-cost high-performance alternatives for a 28 nm CMOS Matching Network (MN). The design was validated by FEM simulations and implemented for the first case in 130 nm SOI technology, and for the second case in 3-layer core-less package technology. The SOI implementation provides a peak output power of 16 dBm, presents an Insertion Loss (IL) of 2dB. The package implementation provides a peak output power of 19 dBm and an IL of 0.6 dB. Measurement results show that the Silicon-on-Insulator (SOI) implementation offers in a Switched Capacitor Power Amplifier (SCPA) peak efficiency of 18% while the implementation with in-package matching network offers a peak efficiency 38 %.