Buffer Design and Eye-Diagram Based Characterization of a 20 GS/s CMOS DAC

Abstract

High-Speed Digital-to-Analog Converters (DACs) are inevitable due to the advent of multi level modulation formats to meet the increasing demand of high data rates in communication systems. In this paper, a 4-bit 20 GS/s DAC has been designed in 90 nm CMOS technology. CMOS based DACs provide a low cost single IC solution as compared to compound semiconductor counterparts by fully integrating digital and RF blocks. In this paper, an on-chip Linear Feedback Shift Register (LFSR) is used to generate the required high-speed broadband data and eye diagram of the DAC output is used for characterization. In order to drive the high capacitive loads along with routing, Electro Static Discharge (ESD) and pad capacitance (≈800 fF) at a speed of 20 GS/s (13.1 GHz bandwidth), a new buffer architecture has also been implemented.