Shallow multiplication circuits

Abstract

Y. Ofman (1963), C.S. Wallace (1964), and others used carry save adders to design multiplication circuits whose total delay is proportional to the logarithm of the length of two numbers multiplied. An extension of their work is presented. A general theory is presented describing the optimal way in which given carry save adders can be combined into carry save networks. Two new designs of basic carry save adders are described. Using these building blocks and the general theory, the shallowest known theoretical circuits for multiplication are obtained.<>