Md Maruf Abir Bappy, Md. Rubel Sarkar, Saad Ibn Hasan, Md Minhajul Azmir, Dewan Mohammed Rashid
{"title":"Design Process and Performance Analysis of Two Stage Differential Op-amp by Varying The Body Biasing in Fully Depleted Silicon On Insulator Technology","authors":"Md Maruf Abir Bappy, Md. Rubel Sarkar, Saad Ibn Hasan, Md Minhajul Azmir, Dewan Mohammed Rashid","doi":"10.1109/iemcon53756.2021.9623233","DOIUrl":null,"url":null,"abstract":"The paper represents the full design process of a two-stage differential operational amplifier (op-amp) as well as a brief behavior analysis of the design. This work also demonstrates the performance variation of the op-amp by changing the potential level of the body biasing terminal in Fully Depleted Silicon on Insulator (FD-SOI) technology. If the FD-SOI technology is used, the performance of the circuit can be varied without changing the parameter of the CMOS (Complementary Metal Oxide Semiconductor) devices related to the physical dimensions (length and width). This paper showed the result of performance variation depending on different back bias connection and explains how FD-SOI technology provides the advantages to the designer in case of limited option of parameter variations. The supply voltage of the designed op-amp was 0.8V and the circuit simulations were done under room temperature, 27° Celsius using Cadence Spectre Analog Design Environment (ADE). The result was varied without any manipulation of device parameter while only change was in bias potential. Due to the variation of bias potential the design performance is varied, the variation of gain is obtained from 34.15dB to 45.76dB, the bandwidth was varied from 3MHz to 7.18MHz at −3dB and leakage was also improved from 30.14μA to 26.02 µA. The phase margin was achieved up to 65.4° from 60.01°. To have a clear view of the performance a table is appended in this paper to demonstrate the advantage of FD-SOI technology in case of op-amp design.","PeriodicalId":272590,"journal":{"name":"2021 IEEE 12th Annual Information Technology, Electronics and Mobile Communication Conference (IEMCON)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE 12th Annual Information Technology, Electronics and Mobile Communication Conference (IEMCON)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/iemcon53756.2021.9623233","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
The paper represents the full design process of a two-stage differential operational amplifier (op-amp) as well as a brief behavior analysis of the design. This work also demonstrates the performance variation of the op-amp by changing the potential level of the body biasing terminal in Fully Depleted Silicon on Insulator (FD-SOI) technology. If the FD-SOI technology is used, the performance of the circuit can be varied without changing the parameter of the CMOS (Complementary Metal Oxide Semiconductor) devices related to the physical dimensions (length and width). This paper showed the result of performance variation depending on different back bias connection and explains how FD-SOI technology provides the advantages to the designer in case of limited option of parameter variations. The supply voltage of the designed op-amp was 0.8V and the circuit simulations were done under room temperature, 27° Celsius using Cadence Spectre Analog Design Environment (ADE). The result was varied without any manipulation of device parameter while only change was in bias potential. Due to the variation of bias potential the design performance is varied, the variation of gain is obtained from 34.15dB to 45.76dB, the bandwidth was varied from 3MHz to 7.18MHz at −3dB and leakage was also improved from 30.14μA to 26.02 µA. The phase margin was achieved up to 65.4° from 60.01°. To have a clear view of the performance a table is appended in this paper to demonstrate the advantage of FD-SOI technology in case of op-amp design.