Design Process and Performance Analysis of Two Stage Differential Op-amp by Varying The Body Biasing in Fully Depleted Silicon On Insulator Technology

Md Maruf Abir Bappy, Md. Rubel Sarkar, Saad Ibn Hasan, Md Minhajul Azmir, Dewan Mohammed Rashid
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引用次数: 1

Abstract

The paper represents the full design process of a two-stage differential operational amplifier (op-amp) as well as a brief behavior analysis of the design. This work also demonstrates the performance variation of the op-amp by changing the potential level of the body biasing terminal in Fully Depleted Silicon on Insulator (FD-SOI) technology. If the FD-SOI technology is used, the performance of the circuit can be varied without changing the parameter of the CMOS (Complementary Metal Oxide Semiconductor) devices related to the physical dimensions (length and width). This paper showed the result of performance variation depending on different back bias connection and explains how FD-SOI technology provides the advantages to the designer in case of limited option of parameter variations. The supply voltage of the designed op-amp was 0.8V and the circuit simulations were done under room temperature, 27° Celsius using Cadence Spectre Analog Design Environment (ADE). The result was varied without any manipulation of device parameter while only change was in bias potential. Due to the variation of bias potential the design performance is varied, the variation of gain is obtained from 34.15dB to 45.76dB, the bandwidth was varied from 3MHz to 7.18MHz at −3dB and leakage was also improved from 30.14μA to 26.02 µA. The phase margin was achieved up to 65.4° from 60.01°. To have a clear view of the performance a table is appended in this paper to demonstrate the advantage of FD-SOI technology in case of op-amp design.
全贫绝缘体上硅两级差分运算放大器的设计过程及性能分析
本文介绍了一种两级差分运算放大器的完整设计过程,并对该设计进行了简要的性能分析。这项工作还展示了在完全耗尽绝缘体上硅(FD-SOI)技术中,通过改变体偏置终端的电位水平来改变运算放大器的性能变化。如果使用FD-SOI技术,可以在不改变CMOS(互补金属氧化物半导体)器件的物理尺寸(长度和宽度)相关参数的情况下改变电路的性能。本文展示了不同背偏置连接的性能变化结果,并解释了FD-SOI技术如何在参数变化选择有限的情况下为设计人员提供优势。所设计的运放的电源电压为0.8V,电路仿真在室温27℃下使用Cadence Spectre Analog Design Environment (ADE)进行。结果在不改变器件参数的情况下发生变化,只改变偏置电位。由于偏置电位的变化,设计性能发生了变化,增益从34.15dB变化到45.76dB,带宽从3MHz变化到7.18MHz,泄漏从30.14μA提高到26.02 μA。相位裕度从60.01°提高到65.4°。为了对性能有一个清晰的认识,本文附加了一个表格来展示FD-SOI技术在运算放大器设计中的优势。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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