Probabilistic IP verification

Abstract

Modern VLSI CAD makes intensively use of core based design and integration of Intellectual Property (IP) to handle the IC design complexity. Several methods for IP integration in today's design flow have been proposed. In this paper we present a new model for verification of designs using IP. We make use of probabilistic algorithms to verify a circuit. Our model allows the IP owners and creators to keep all detailed information about the design, while the designer can probabilistically verify his design.