A single-channel 5bit 333MS/s asynchronous digital slope ADC based on CMOS technology

Abstract

This project design and present a 5-bit 333MS/s digital slope ADC (analog-to-digital converter. It is implemented and simulated with Cadence tool in SMIC 55nm CMOS technology. The power supply is 1.2 V and the improved delay cells are used which can shorten the delay time to 50ps. In addition, a self-disabled comparator is used to save power. When the peak-to-peak value of input is 0.4V, the SNDR(Signal to Noise and Distortion Ratio) is 28.19 dB, ENOB(Effective Number of Bits)is 4.39 bit, SFDR(Spurious Free Dynamic Range) is 35.87 dB, SNR(Signal-to-Noise Ratio)is 31.47dB.