Methodology for interference analysis during early design stages of high-performance mixed-signal ICs

Abstract

A simulation methodology to predict and mitigate interferences between different subsystems in complex mixed-signal system-on-chip ICs at the early stages of a design project is presented. Different aspects of the analysis flow and abstraction levels of the models are discussed. The impact of the floorplan and design choices on circuit performance and the relative contribution of different coupling mechanisms are shown on a number of examples. Special attention is paid to on-chip and package coupling effects. The methodology has been validated with silicon measurements and has been successfully applied in the design process of NXP products.