Hardware implementation of a neural network based path planning algorithm by using the VHDL

Abstract

This paper presents a new approach for designing a neural network based path planning algorithm in an integrated circuit by using the VHDL. VHDL is the name of the IEEE 1076 hardware description language standard for very high speed digital circuit design. The structure of the VHDL provides a convenient construct for the implementation of neural network into electronic hardware. In addition, with VHDL analyzer and logic synthesis software, hardware prototypes can be implemented in ASIC, especially field programmable gate array, automatically.<>