Parallel statistical capacitance extraction of on-chip interconnects with an improved geometric variation model

Wenjian Yu, Chao Hu, Wangyang Zhang
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引用次数: 14

Abstract

In this paper, a new geometric variation model, referred to as the improved continuous surface variation (ICSV) model, is proposed to accurately imitate the random variation of on-chip interconnects. In addition, a new statistical capacitance solver is implemented to incorporate the ICSV model, the HPC [5] and weighted PFA [6] techniques. The solver also employs a parallel computing technique to greatly improve its efficiency. Experiments show that on a typical 65nm-technology structure, ICSV model has significant advantage over other existing models, and the new solver is at least 10X faster than the MC simulation with 10000 samples. The parallel solver achieves 7X further speedup on an 8-core machine. We conclude this paper with several criteria to discuss the trade-off between different geometric models and statistical methods for different scenarios.
基于改进几何变化模型的片上互连并联统计电容提取
本文提出了一种新的几何变化模型,即改进的连续表面变化(ICSV)模型,以准确地模拟片上互连的随机变化。此外,还实现了一种新的统计电容求解器,结合了ICSV模型、HPC[5]和加权PFA[6]技术。求解器还采用了并行计算技术,大大提高了求解效率。实验表明,在典型的65nm工艺结构上,ICSV模型比其他现有模型具有显著的优势,并且新的求解器比具有10000个样本的MC模拟快至少10倍。并行求解器在8核机器上实现了7倍的进一步加速。最后,我们用几个准则来讨论不同几何模型和统计方法在不同场景下的权衡。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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