Via Design Optimization for Server Applications

Abstract

As the technology continues scaling down and the data rate is increasing dramatically, PCB design has become more challenging than ever. Keeping track of signal and power integrity becomes a requirement for PCB designers in order to meet the product development time and reduce the overall cost. In high speed IO signals, vias play a critical role for the signal integrity quality. It is important to design the via impedance within a certain range. Due to server products have a higher thickness of PCB design than other consumer products, and its data rates are on the cutting edge, the need for the via optimization is acquired. In this work, the investigate on the via impedance control is studied to optimize the via design on the pitch, individual and oval antipad shapes. And the further analyses of via design parameters are examined to understand the effects of dominance.