{"title":"Low complexity GMSK modulator and demodulator for integrated circuit implementation","authors":"S. McGrath, C. Burkley","doi":"10.1109/VETEC.1990.110384","DOIUrl":null,"url":null,"abstract":"The design of a reduced-complexity modulator and demodulator using Gaussian minimum shift keying (GMSK) is presented. Both modulator and demodulator follow the European Conference of Postal and Telecommunications Administrations (CEPT), Group Special Mobile (GSM) recommendations. A single ROM modulator circuit and a coherent demodulator using De Buda (1972) clock and carrier techniques are used to give reduced complexity designs. The demodulator is a coherent receiver that uses phase-locked loops in the clock and carrier recovery circuits. Both the modulator and demodulator designs give satisfactory performance at reduced complexity, and are suitable for implementation on silicon.<<ETX>>","PeriodicalId":366352,"journal":{"name":"40th IEEE Conference on Vehicular Technology","volume":"248 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"40th IEEE Conference on Vehicular Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VETEC.1990.110384","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
The design of a reduced-complexity modulator and demodulator using Gaussian minimum shift keying (GMSK) is presented. Both modulator and demodulator follow the European Conference of Postal and Telecommunications Administrations (CEPT), Group Special Mobile (GSM) recommendations. A single ROM modulator circuit and a coherent demodulator using De Buda (1972) clock and carrier techniques are used to give reduced complexity designs. The demodulator is a coherent receiver that uses phase-locked loops in the clock and carrier recovery circuits. Both the modulator and demodulator designs give satisfactory performance at reduced complexity, and are suitable for implementation on silicon.<>