Gate Driver Chip-Set using Low Volt-Second Pulse Transformer for Galvanic Signal Isolation

Abstract

This paper presents the design of an isolated gate driver system using a low volt-second differential pulse scheme to enable the use of a thin-film magnetics-on-silicon coupled solenoid transformer. The transformer was designed for a CMOS compatible back-end-of-line (BEOL) process to ultimately enable monolithic integration with the gate driver. The transformer enables primary side or functional isolation of the gate driver with very low propagation delay and low CIO. The design of a prototype custom 130 nm CMOS gate-driver signal-coupling chipset around this transformer achieved operation with sub 10 V.ns gate driver signal pulses. The prototype system simulated a common-mode transient immunity (CMTI) to a switch-node slewing rate of 34 V/ns but simulations on an improved design achieved CMTI of 200 V/ ns. The gate driver system design presented is applicable for advanced heterogeneous integration of thin-film magnetically isolated gate driver chipsets for a variety of power switch technologies including DMOS, GaN, and SiC.