A prover for VHDL-based hardware design

Abstract

Surveys a self-contained part of the ESPRIT-project "FORMAT", which develops a prover for VHDL-based hardware design. Notable is the use of a graphical specification language called STD (Symbolic Timing Diagrams), which can be seen as a visual dialect of temporal logic. The heart of the prover is built by two powerful industrial verification tools: A (compositional) symbolic model checker (developed by SIEMENS), and the LAMBDA-theorem prover (developed by AHL). The aim of this paper is to describe (1) the various tools integrated in the prover, (2) the graphical specification language STD with its associated design methodology, and (3) to explain how proofs about generic (parameterized) designs are performed in the prover, using a combination of automatic and interactive reasoning.