Error detection enhancement in COTS superscalar processors with event monitoring features

Abstract

Increasing use of commercial off-the-shelf (COTS) superscalar processors in industrial, embedded, and real-time systems necessitates the development of error detection mechanisms for such systems. This shows an error detection scheme called committed instructions counting (CIC) to increase error detection in such systems. The scheme uses internal performance monitoring features and an external watchdog processor (WDP). The performance monitoring features enable counting the number of committed instructions in a program. The scheme is experimentally evaluated on a 32-bit Pentium/spl reg/ processor using software implemented fault injection (SWIFI). A total of 8181 errors were injected into the Pentium/spl reg/ processor. The results show that the error detection coverage varies between to 90.92% and 98.41%, for different workloads.