Design of Datapath Circuits for a Bit-Parallel 8-bit RSFQ Microprocessor

Pei-Yao Qu, Guangming Tang, Xiao-Chun Ye, D. Fan, Zhimin Zhang, Ning-Hui Sun
{"title":"Design of Datapath Circuits for a Bit-Parallel 8-bit RSFQ Microprocessor","authors":"Pei-Yao Qu, Guangming Tang, Xiao-Chun Ye, D. Fan, Zhimin Zhang, Ning-Hui Sun","doi":"10.1109/ISEC46533.2019.8990911","DOIUrl":null,"url":null,"abstract":"Rapid single-flux-quantum (RSFQ) is expected to be the next generation integrated circuit technology because of its ultra-high-speed with ultra-low-power consumption. We propose datapath circuits for an 8-bit bit-parallel RSFQ microprocessor. The proposed datapath circuits process 8-bit data each clock cycle. Seven instructions are executed in the datapath, including ADD, ADDI, IN, OUT, LOADI, SRL and MOV. The datapath circuits consist of eight input ports, eight output ports, five multiplexers (MUXs), two 8-bit data registers and one 8-bit bit-parallel arithmetic logic unit (ALU). The datapath circuits contain 12 pipeline stages and 2993 JJs based on the Open Dataset of CONNECT Cell Library for AIST ADP2 without considering wiring cells. We perform digital simulation of the proposed datapath circuits. The simulation results show correct operation with the assumed frequency of 20 GHz.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE International Superconductive Electronics Conference (ISEC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISEC46533.2019.8990911","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

Abstract

Rapid single-flux-quantum (RSFQ) is expected to be the next generation integrated circuit technology because of its ultra-high-speed with ultra-low-power consumption. We propose datapath circuits for an 8-bit bit-parallel RSFQ microprocessor. The proposed datapath circuits process 8-bit data each clock cycle. Seven instructions are executed in the datapath, including ADD, ADDI, IN, OUT, LOADI, SRL and MOV. The datapath circuits consist of eight input ports, eight output ports, five multiplexers (MUXs), two 8-bit data registers and one 8-bit bit-parallel arithmetic logic unit (ALU). The datapath circuits contain 12 pipeline stages and 2993 JJs based on the Open Dataset of CONNECT Cell Library for AIST ADP2 without considering wiring cells. We perform digital simulation of the proposed datapath circuits. The simulation results show correct operation with the assumed frequency of 20 GHz.
位并行8位RSFQ微处理器的数据路径电路设计
快速单通量量子(RSFQ)以其超高速、超低功耗的特点,有望成为下一代集成电路技术。我们提出了一个8位位并行RSFQ微处理器的数据通路电路。所提出的数据通路电路每个时钟周期处理8位数据。在数据路径中执行7条指令,包括ADD、ADDI、in、OUT、LOADI、SRL和MOV。数据路径电路由8个输入端口、8个输出端口、5个多路复用器(mux)、2个8位数据寄存器和1个8位位并行算术逻辑单元(ALU)组成。数据路径电路包含12个管道级和2993个js,基于AIST ADP2的CONNECT Cell Library开放数据集,不考虑布线单元。我们对所提出的数据路径电路进行了数字仿真。仿真结果表明,在假设频率为20 GHz的情况下,系统运行正常。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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