Towards spiking neuromorphic system-on-a-chip with bio-plausible synapses using emerging devices

Abstract

Large-scale integration of CMOS mixed-signal integrated circuits and nanoscale emerging memory devices, such as the resistive RAM (RRAM) crosspoint arrays, can enable a new generation of Neuromorphic computers that can alleviate the von Neumann bottleneck, and be applied to a wide range of cognitive computing tasks1. Such hybrid Neuromorphic System-on-a-chip (NeuSoC) architectures will result in deep learning capability at chip-scale form factors, and several orders of magnitude reduction in energy consumption. Progress in this area has been impeded as the performance of these emerging devices falls short of the expected behavior from the idealized analog synapses, or weights, and new learning algorithms are needed to take advantage of the devices. To address these, we present a pathway to realize spike-based mixed-signal neuromorphic architectures; bottom-up from device arrays, circuit motifs, to semi-supervised algorithms that can realize large scale deep learning, autonomous control, sensor fusion and inference systems with 'brain-like' energy-efficiency.