A 28 mW, 1.5 V GPS receiver in 0.25 μm silicon-on-sapphire CMOS process

Abstract

This paper describes a 28 mW, 1.5 V Global Positioning System (GPS) radio receiver chip implemented in a 0.25 μm silicon-on-sapphire CMOS process. The receiver uses a low IF architecture and achieves a cascaded noise figure of 3.5 dB including the RF SAW filter. The design takes advantage of the matching network integration capabilities and superb isolation properties of Peregrine's UltraCMOStrade silicon-on-sapphire process technology.