Hardware implementation of a strong pseudo-random numbers generator with an application to image encryption

Abstract

This paper suggests a high-performance FPGA implementation of a strong pseudo-random numbers generator for several applications mainly in the security domain. An improved PRNG utilizing the Lorenz chaotic map is propounded. Then, using the Xilinx System Generator software of Xilinx society an FPGA architecture of the DPRNG is developed. Next, the hardware DPRNG is implemented on an FPGA-Zynq resulting in low resource utilization, a good frequency of 194.714 MHz, and high throughput of 25702 Mbps. The NIST 800-22 SP test suite result demonstrates that the suggested hardware DPRNG allows for generating high-quality random numbers. It provides a strong key with a high space. In addition, an application of the hardware DPRNG for image encryption is presented. The experimental results show better results when compared to other recent works.