{"title":"Design of a high gain, Temperature Compensated Biomedical Instrumentation Amplifier for EEG Applications","authors":"Aditi Jain, Kavindra Kandpal","doi":"10.1109/ISCO.2017.7856001","DOIUrl":null,"url":null,"abstract":"This paper proposes a high gain, low power instrumentation amplifier (IA) for EEG signal processing. A three opamp instrumentation amplifier has been designed by using sub-threshold three-stage op-amps with PMOS input. NMOS transistors operating in the triode region have been used to replace the passive resistors of IA. This eliminates the problems of mismatch, temperature dependency and large area consumption, at the same time taking advantage of the high CMRR and DC offset cancellation properties of conventional IA. A BGR circuitry with temperature coefficient of 420 ppm/°C is used to bias the opamp. The instrumentation amplifier is simulated in Cadence Virtuoso 180nm CMOS technology by using a supply voltage of 1V. It achieves a Gain of 96.4dB, Bandwidth of 400 KHz, input-referred noise voltage of 610nV/√ Hz, CMRR in the range of 60dB and power consumption about 53.7 µW.","PeriodicalId":321113,"journal":{"name":"2017 11th International Conference on Intelligent Systems and Control (ISCO)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 11th International Conference on Intelligent Systems and Control (ISCO)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCO.2017.7856001","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This paper proposes a high gain, low power instrumentation amplifier (IA) for EEG signal processing. A three opamp instrumentation amplifier has been designed by using sub-threshold three-stage op-amps with PMOS input. NMOS transistors operating in the triode region have been used to replace the passive resistors of IA. This eliminates the problems of mismatch, temperature dependency and large area consumption, at the same time taking advantage of the high CMRR and DC offset cancellation properties of conventional IA. A BGR circuitry with temperature coefficient of 420 ppm/°C is used to bias the opamp. The instrumentation amplifier is simulated in Cadence Virtuoso 180nm CMOS technology by using a supply voltage of 1V. It achieves a Gain of 96.4dB, Bandwidth of 400 KHz, input-referred noise voltage of 610nV/√ Hz, CMRR in the range of 60dB and power consumption about 53.7 µW.