Viterbi decoding with dual timescale traceback processing

Abstract

A new approach to traceback processing in Viterbi decoders is presented. The approach reduces memory requirements as compared to previous approaches by using different speeds during acquisition of the best trellis path and the subsequent decoding of a block of data. This dual timescale approach allows in-place updating of the stored information and matches the constraints of commodity semi-custom technologies, where (at the considered high dock rates) write accesses to a RAM usually require more than one clock cycle.