40nm Donut Scan Failed Induced by Active Drain/Source Stress Issue

Abstract

40nm devices suffered donut scan bin failure and result in yield loss, and these failures are particularly occurs in devices with high-Vt nMOSFET (HVTN) cores. These failures are mainly caused by combination of two factors: HVTN manufacturing process and Active (RX) layer design. Based on studies, reduce the RX CD and introduction of N2 implant in HVTN process step help to reduce yield loss.