Influence of the Layout Parasitic Effects on the Performance of Current Mode Amplifier Designed Using 32nm CMOS Technology

Abstract

This paper investigates the influence of layout parasitic RC elements on the main parameters of a current mode amplifier designed in deep sub-micron CMOS technology - 32nm bulk CMOS process. Three distinct layout designs of the same amplifier circuit are implemented and compared by re-simulation. The effect of parasitic elements is investigated and estimated in the most appropriate layout. The statistical distribution of the main amplifier parameters due to process variation is received by Monte Carlo analysis.